1. Field of the Invention
The present invention relates to dielectric charge trapping memory technology arranged for nonvolatile and dynamic random access applications.
2. Description of Related Art
Current flash memory products are typically implemented using a NOR architecture or a NAND architecture.
For NOR architecture flash, the memory transistors are connected in parallel, so that large reading current can be provided (typically larger than 20 μA). The large reading current provides fast random access read applications (typically 70-100 nsec for single bit reading). However, for NOR Flash, programming usually employs channel hot electron (CHE) injection. CHE programming consumes relatively large amounts of power, limiting the total programming throughput for NOR Flash. Moreover, hot-carrier injection often has relatively poor program and erase P/E endurance, since the high-energy carriers easily damage the tunnel oxide.
For NAND Flash, the memory transistors are connected in series. Typically a total of 16 or 32 transistors are connected in series, and the reading current must flow through all the series connected cells, greatly reducing the reading current. Typically the read current in such devices is smaller than 1 μA, and the random access read time for single bit is about 20 μsec. Therefore, NAND Flash has the drawback that random access read is impractical. On the other hand, NAND Flash can utilize +/−Fowler-Nordheim (FN) tunneling for the erase and program operations. FN tunneling operation has very low power consumption, which facilitates high-speed and low-power applications. Also, devices using FN tunneling operation generally have much better P/E endurance.
However, NOR and NAND Flash do not support random bit-by-bit erase operations. For flash operations, a sector or page must be erased simultaneously. Therefore, Flash memory has not been applied for applications requiring random read and write operation at high speeds.
So-called AND Flash architectures have also been developed for random access applications, using silicon on insulator SOI structures or “assist gate” structures to provide independent source and drain lines for each column of cells. See, U.S. Patent Application Publication No. 2007/0057307, by Shum et al., published 15 Mar. 2007; and Hitoshi et al., “A 140 mm2 64 Mb AND Flash Memory with 0.4 mm Technology”, 1996 IEEE International Solid-State Circuits Conference, pp. 34-36 (1996). However, slow erase speeds still limit application of AND architecture devices to applications that do not require high speed, random write access.
Dynamic random access memory DRAM is another class of memory device. The scaling of the conventional one-transistor, one capacitor 1T1C DRAM memory has become very difficult since the cell capacitance is not scalable. In recent years many one transistor 1T DRAM cells have been proposed. One attractive device is the floating body cell (FBC) described by Y. Minami, et al, in IEDM Tech. Dig., 2005, pp. 317-320, that utilizes the transient charge storage in the floating body of an SOI MOSFET. However, it is very difficult for an FBC to achieve good data retention because junction leakage easily bleeds the storage node. Moreover, large channel current (>50 μA) and thus high power is needed to generate impact ionization to program the cell.
Charge-trapping devices such as SONOS with ultra-thin (˜1 nm) bottom tunnel oxide described by C. H. J. Wann, et al, in IEDM Tech. Dig., 1995, pp. 867-870, have also been proposed for DRAM. Direct tunneling through thin oxide provides fast program/erase speed at low voltage. However, during program/erase operation current flows through the gate oxide (tunnel oxide) and causes damage to the gate oxide. Therefore, SONOS devices have relatively poor endurance of <107 cycles.
It is desirable to provide an integrated circuit memory device that supports high density arrays, along with high-speed random access suitable for nonvolatile memory and for DRAM applications.